1. Technical Field
The present invention relates generally to data communications. More particularly, the present invention relates to circuitry for high-speed data links.
2. Description of the Background Art
High-speed data links are used to communicate data between devices in a system. Serial interface protocols have been developed at increasingly fast data rates for such high-speed links. Currently, the data signal for most high-speed serial links use just two voltage levels (amplitudes) to convey information: a high level and a low level. The high level may be interpreted as a logical one, and the low level may be interpreted as a logical zero. Such signaling is sometimes referred to as “non-return-to-zero” (NRZ) data signaling. In NRZ signaling, one symbol provides one bit of information within one unit interval (UI).
Instead of using just two levels, multi-level amplitude signaling uses several (at least three) distinct voltage levels. Such multi-level amplitude signaling, which is sometimes referred to as pulse amplitude modulation (PAM) signaling, communicates more than one bit of information per symbol. Hence, for the same symbol rate, PAM signaling provides a higher effective data rate than NRZ signaling.
Unfortunately, transceiver complexity generally increases if, instead of NRZ signaling, PAM signaling is implemented. For example, a high-speed analog-to-digital converter (ADC) circuit is typically implemented at the front end of the receiver to digitize the PAM signal. However, such a high-speed ADC circuit generally requires a relatively large area to implement and typically consumes a large amount of power.